1. Field of the Invention
The invention relates to a method for forming a gate electrode in a semiconductor device and, more particularly, a method for forming a gate electrode in a semiconductor device that includes a self-aligned contact (SAC) process for forming a damascene tungsten (W) gate.
2. Description of the Related Art
In general, a gate electrode is an electrode utilized to control a single MOS transistor and is most commonly formed from a doped polysilicon layer. Utilizing a polysilicon gate electrode is advantageous in that the process for forming such gates is well known and stable. However, it is known that polysilicon gates have certain drawbacks such as a high resistivity and/or a depletion phenomenon. For these reasons, polysilicon is unsuitable as the gate material in highly integrated semiconductor devices.
In the past, in order to make up for the drawbacks of the doped polysilicon gate, a metal film having a high electric conductivity and good thermal stability was used as a material for gate electrodes. The preferred metal films exhibited a work function located in a mid-band gap of silicon and could, therefore, provide a threshold voltage that is symmetric between NMOS and PMOS regions. Such metal films have included tungsten (W), tungsten nitride (WN), titanium (Ti), molybdenum (Mo), tantalum (Ta), aluminum (Al) and copper (Cu).
However, the metal films has a difficulty to be patterned into a gate electrode form. Also, during the ion implantation process necessary to form the source and drain regions, the surface of the metal film may be damaged. Moreover, during the thermal processing necessary to activate the implanted impurity ions to form the source and drain regions, a thermal load is exerted on the gate electrode, causing variations in the characteristics of the resulting semiconductor devices.
In order to solve the above-mentioned problems, a method has been proposed for forming a gate electrode using a metal film in accordance with a damascene technique. This technique will be described with reference to FIGS. 1A to 1E.
As shown in FIG. 1A, a buffer gate insulating film 2, polysilicon layer 3a, and a hard mask layer 3b are sequentially formed on a semiconductor substrate 1 where a field-oxidized film (not shown) has been formed to a desired height to define active and isolation regions. The hard mask layer 3b is then patterned and etched in the form of a gate electrode. The polysilicon layer 3a and the buffer gate insulating film 2 are then etched using the hard mask 3b as an etch mask to have to form dummy gate g. Spacers 4 are then formed at both sides of each dummy gate g utilizing a conventional method. Impurity ions are then implanted into the exposed portion of semiconductor substrate 1 outside of the spacers 4 to form source and drain regions 5.
As shown in FIG. 1B, an interlayer insulating film 6 is then deposited over the resulting structure of the semiconductor substrate 1 and dummy gate electrodes g. The interlayer insulating film 6 is then subjected to a chemical mechanical polishing (CMP) process to remove a portion of the insulating interlayer insulating film and expose the top surfaces of the dummy gates g.
As shown in FIG. 1C, the dummy gates g, that is, the hard mask layer 3b, the polysilicon layer 3a, and the buffer gate insulating film 2, are then selectively etched. Consequently, only the interlayer insulating film 6 and the spacers 4 remain on the semiconductor substrate 1.
As shown in FIG. 1D, a gate insulating film 7 and a metal film 8 are sequentially formed on the exposed surface portions of the semiconductor substrate 1, the inner sidewall surfaces of the spacers 4 and the top surface of the interlayer insulating film 6.
Finally, as shown in FIG. 1E, the metal film 8 and the gate insulating film 7 are chemically and mechanically polished to expose the top surfaces of the interlayer insulating films 6, thereby forming damascene metal gate electrodes 8a in respective regions where the dummy gates had been formed.
The damascene metal gate electrodes 8a thus obtained provide certain advantages by deferring the gate electrode formation until after the transistor source/drain regions have been formed. For example, it is possible to avoid both the difficulties associated with patterning metal layers, plasma damage that can occur during the etch process, and damage from the ion implantation processes, and thermal damage that can occur during the subsequent thermal process used to activate the source/drain regions.
FIG. 2 is a cross-sectional view illustrating problems involved in conventional gate electrodes.
Conventionally, the manufacture of a memory device involves a process for forming contact openings for bringing the sources/drains into contact with the desired bit lines and storage lines after a formation of transistors.
In the manufacture of highly integrated memory devices, misalignment problems inevitably occur in association with the contact patterning process. FIG. 2 shows a method conventionally used to compensate for such misalignment problems. In accordance with the method shown in FIG. 2, a gate electrode patterning process is only after a hard mask layer 3b has been deposited over a gate electrode g and nitride film spacers 4 have been formed on the sidewalls of the gate electrode g to surround the gate electrode g. As a result, as shown in FIG. 2, even if contacts 9 are misaligned during the exposing process, the spacers 4 and the hard mask layer 3b serve as etch barriers and insulators, whereby the formation of being short-circuits between the gate electrode and a bit line or storage line can be suppressed.
In the case of the gate structure formed by using the damascene process as shown in FIGS. 1A to 1E, however, it is impossible to prevent the metal gate electrode 8a from being prone to short-circuits with a bit line or storage line in the event of contact misalignment because there is no nitride film metal gate electrode 8a that can serve as an etch barrier.
Therefore, the present invention has been made in order to solve the above-mentioned problems in the prior art. An object of the present invention is to provide a method for forming a gate electrode in a semiconductor device in which a nitride film is formed over damascene metal gate electrodes, thereby protecting the gate electrodes from being short-circuited to a bit line or storage line even if the contact pattern is misaligned.
In order to achieve the above object, the method for forming a gate electrode in a semiconductor device according to the present invention is characterized by the steps of:
forming a damascene metal gate electrode provided with spacers at respective sidewalls thereof;
recess-etching the damascene metal gate electrode to form a trench;
depositing a nitride film over a structure obtained after the formation of the trench;
blanket-etching the nitride film with a dry etch without using a mask;
depositing an interlayer insulating film over a structure obtained from the blanket-etching step; and
subjecting a structure obtained after the deposition of the interlayer insulating film to a patterning and etch process to partially expose respective surfaces of source and drain regions formed in the structure, thereby forming contact openings.
The damascene metal gate electrodes are preferably made from a material selected from a group consisting of tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), tantalum (Ta), and tantalum nitride (TaN) with a preferred thickness of 2,000-2,500 xc3x85.
The spacers are made from a nitride film with a deposited thickness of between 100 to 1,500 xc3x85.
The trench has a preferred depth of 500 to 1,000 xc3x85.